The present invention relates to the field of integrated circuit design checking; and more specifically, it relates to an efficient method for analyzing the timing, noise, and power consumption of logic networks in such integrated circuits prior to physically implementing the circuitry in hardware.
Integrated circuit devices are comprised of large numbers of networks linked together to perform various logic functions. They are typically implemented in hardware form on silicon dies using solid state integrated circuit technology of which many types exist, very large scale integration (VLSI) being an example. A hierarchical implementation in such technology exists. The basic elements are the transistor, resistor, capacitor, or inductor, usually built in the silicon. One or more of these basic elements, or combinations thereof are electrically coupled to form the next higher elements, logic elements or gates, that perform simple to moderate logic tasks. When these elements are implemented in silicon, unwanted but often unavoidable parasitic elements such as capacitors, resistors, and inductors are created which can change the designed performance of higher order elements in the design. Other non-electrical elements such as mechanical linkages and thermal resistances may also be created and may have an effect on other aspects of the design, such as its reliability. In the next higher element, one or more gates are then electrically coupled to form logic networks that perform more complicated logical tasks. The electrical interconnection is implemented in hardware in conductive lines in wiring layers on the integrated circuit. The signals run from gate to gate in a network along these conductive wiring layers. Several problems arise in these interconnection designs that can adversely effect network or integrated circuit performance.
First the implementation of these wires introduces additional parasitic elements which can add unexpected delays to the signal propagation through the network. Second, signals running in one wire in close proximity to a second can couple and create a false signal on the second wire. Third, local voltage levels in the power grid can drop in some networks, making them more sensitive to noise on the signal wire. And fourth networks, circuit gates or even individual transistors and resistors can draw more current than anticipated because of duty cycle or other reasons, increasing power consumption. This increased power consumption often leads to local voltage drops which increase noise sensitivity.
Because it is expensive and time consuming to complete a physical implementation of integrated circuit design, find problems, redesign, and rebuild, it is advantages to do design analysis and design correction before implementation.
FIG. 1 is a flow diagram of outlining the general prior art method of integrated circuit design checking employed before first pass die layout is complete. The design is reduced to a design netlist 10 upon which circuit analysis 12 is performed. Design netlist 10 contained the circuit design information. The circuit analysis step 12 provides data so fixes can be calculated in step 14, and changes made to the netlist 10. The process is repetitive and much of the fix calculation is manual. As applied to timing analysis, this method uses estimated parasitics, supplied by the designer based on the designers prediction of relative placement of layout elements. Often this input is provided only for those networks where parasitics are believed to impact the critical timing.
FIG. 2 is a flow diagram outlining the general prior art method of integrated circuit design checking for analyzing time delays after first pass die layout is complete. The netlist 10 and a shapes file 16 are used to extract or calculate the parasitics in step 18 for each network in the design. Shapes file 16 contains the layout information. The circuit analysis software of step 12 then supplies data so the fixes can be calculated in step 14. These fixes are fed back to the design netlist 10 and the shapes file 16. While the flow of FIG. 2 has the advantage of providing more accurate delay data, it is a very time consuming. Often this process is 7 times longer than the method of illustrated in FIG. 1.
To illustrate the range of modeling that can be used for parasitic extraction the examples of FIGS. 3 through 5 are instructive. FIG. 3 is a schematic diagram of a simple network using a simple resistance/capacitance value to represent anticipated parasitic elements, as might be provided by a designer or a pre-layout estimation tool for analyzing timing delays through the network. In FIG. 3 network 20 has input 22 stages 24A, 24B, and 24C, and output 26. The parasitic RC delay is modeled by the resistor 28 and capacitor 29 between stages 24B and 24C. FIG. 4 is a schematic diagram of a simple network using a simple grounded capacitance parasitic elements for analyzing timing delays through the network. In FIG. 4 network 30 has input 32 gates 34A, 34B, and 34C, and output 36. Designers can supply the parasitic as an RC delay comprised of grounded capacitors 38A, 38B and 38C combined with the output impedances of stages 34A, 34B, and 34C, respectively. FIG. 4 is illustrative of another example typical of the parasitics that might be supplied by a designer or early estimation tool for the analysis shown in FIG. 1 and described above.
FIG. 5 is a schematic diagram of a simple network using a complex resistance and capacitance parasitics model for analyzing timing delays through the network; FIG. 6 is a schematic diagram of a simple network. In FIG. 5 network 40 has input 42 gates 44 and 46 and output 48. The extracted parasitics include resistor/capacitor pairs 51A/51B and 52A/52B, which introduce additional delay between input 42 and gate 44. The extracted parasitics further include resistor/capacitor pairs 53A/53B, 54A/54B, and 55A/55B between gates 44 and 46 as well has line to line capacitor 50, which also introduce additional delay. The extracted parasitics still further include resistor/capacitor pairs 56A/56B, 57A/57B, and 58A/58B, which introduce additional delay between gate 46 and output 46. This model, while supplying very accurate parasitics for delay or noise or power analysis, leads to very time consuming runs for the circuit analysis software used with this level of parasitic extraction. However simpler parasitic extractions as shown in FIGS. 3 and 4 and described above, when applied to all nets, can reduce analysis accuracy to an unacceptable degree. The alternative of using manual selection of some networks for the complex models and others for simple parasitic extraction introduces the risk of human error.
In today""s environment the size of elements on semiconductor devices is decreasing, thus the number of elements in an integrated circuit design are increasing making long run times longer and more unacceptable. At the same time, new technologies, circuit design styles, and scaling mean the impact of parasitics on timing, noise, and power grids is increasing and more accurate analysis is required. Therefore there exists a need for a method to provide accurate integrated circuit timing, noise and power design checking in less time.
The present invention provides a method of selectively reducing the complexity of individual network and combined network analysis in an integrated circuit design thus reducing runtimes, while controlling the loss of accuracy of the resulting analysis. The present invention employs a circuit analysis technique suitable for performing timing delay, noise sensitivity, or power consumption analysis.
The invention provides a method of selectively reducing the complexity of the extracted netlist, and thus analysis runtimes, while controlling the loss of accuracy of the resulting analysis. A preliminary analysis is used to divide the range of possible characteristics for each net into a range in which the net definitely would not cause a constraint violation in the resulting analysis, a range in which the net definitely would cause a constraint violation in the resulting analysis, and an intermediate range in which it cannot be easily determined whether or not the net would cause a constraint violation in the subsequent analysis. Each net is then passed through a series of successively more accurate and expensive screens, and successively more accurate and expensive estimates for the net characteristics are determined, until it can be determined whether or not the net will cause a constraint violation in the subsequent analysis. The goal is to use the minimum accuracy necessary for each net. The final and most accurate estimate of net characteristics is used only for those nets which cannot be definitively classified using previous screens and characteristic estimates. The result is a much reduced data volume and complexity while maintaining overall accuracy of the analysis.
The method comprises the steps of calculating a first performance parameter by analyzing the network""s sensitivity to a signal applied to the network; comparing the first performance parameter to one or more rules to determine a first pass condition and writing the value of first performance parameter to a netlist file in response to a pass to the first pass condition; followed by calculating a second performance parameter based on a first network model to determine a second pass condition in response to a fail to said first pass condition and writing the second performance parameter to the netlist file in response to a pass to said second pass condition or writing an error flag to the netlist file in response to a fail to said second pass condition. Instead of terminating the analysis after the second performance factor has been determined, additional performance parameters may be determined using increasing complicated network models and refined estimates of the sensitivity value.
The present invention has the advantage of using the minimum accuracy necessary to determine timing delays, noise sensitivity or power consumption for individual networks or each network in an integrated circuit design. The result is a reduced data volume and reduced run time in subsequent dependent analysis steps. Yet it maintains overall accuracy of the analysis.